As opposed to planar complementary metal oxide semiconductor (CMOS) devices, vertical field effect transistors (VFETs) are oriented with a vertical fin channel disposed on a bottom source and drain, and a top source and drain disposed on the fin channel. VFETs are being explored as a viable device option for continued CMOS scaling beyond the 7 nanometer (nm) technology node.
However, there are some notable challenges associated with scaled designs. For instance, as feature sizes shrink the current drivability of the device can become degraded, negatively impacting device speed and overall performance.
Therefore, techniques for enhancing current drivability in VFET designs would be desirable.